The present invention generally relates to integrated devices having logic matrices, and more particularly, to a programmable arrangement for selectively switching a logic matrix between a low power, stand-by state, and a high power, full-speed mode in response to a wake-up pulse which is generated in different manners as selected by the user.
Typically, most integrated logic circuits employed large matrices of identical elements, such as PROMs, programmable logic arrays, RAMs and the like, which exhibit an almost constant speed-power product for a given process. Consequently, such circuits, when operating at high speeds, also consume considerable amounts of power whereas circuits designated for low power operation are significantly slower. An example of such a speed-power dependency is diagrammatically illustrated in FIG. 1 for programmable array logic circuits (PAL).
The low or zero power circuits satisfy a market segment where low average operating current must be kept to a minimum, such as for example, battery operated devices. High power circuits address that segment of the market in which the minimum required speed performance of the circuit takes precedence over the power consumption. However, in both instances, and particularly in the case of CMOS circuits, the current consumption of the circuits, when operated at full speed, is essentially the same for a given process.
Low power circuits with internal matrices are known which maintain their low, stand-by currents by turning on the power to the matrix only when signal activity is detected at the input to the matrix. This approach requires application of special circuits, such as for example, edge detectors or edge catchers, which monitor the inputs to the circuit and generate a matrix power-up pulse whenever any of the inputs change state. Since such an activity consumes significant amounts of time, the overall latency of such a circuit also increases. Conversely, high-speed circuits attain their speed advantage by keeping the matrices powered at all times, and therefore eliminate the delay associated with edge detection and the generation of a matrix power-up pulse. However, such arrangements result in high power consumption which, in some applications, is detrimental.
Additionally, power-up arrangements for logic matrices are known which permit the user to turn-on the power to the matrix as desired. Such arrangements however, do not permit the use to select the mode by which the logic matrix is powered-up. Thus, if a dedicated input is needed to generate the wake-up pulse and the logic matrix is constructed such that a power-up state is selected by a specific address or product term, the logic matrix would necessarily need to be replaced which is costly both in time and materials.
Accordingly, it is an object of the present invention to provide an arrangement for integrated devices having logic matrices which can be programmed by a user to operate in a number of different modes to switch between a high power, full-speed operational state, and a low-power, stand-by state in dependence upon different processing requirements.
It is another object of the present invention to provide an arrangement wherein the switching between the high power and low power modes is determined by the user without the need for edge detectors and the resulting delay in the power-up of the matrix.
It is yet another object of the present invention to provide an arrangement for selectively switching a logic matrix between a low power, stand-by state and a high power, full speed state, wherein the arrangement is programmable to operate in response to at least a specific address or product term as well as to a wake-up pulse applied to a dedicated input of the matrix.
The present invention can be advantageously applied where components of a digital system operate at full speed for short periods of time in dependence upon different processing requirements, spending the remaining time in an idle state.
Thus, in accordance with the teachings of the present invention, there is provided a programmable speed/power arrangement for an integrated device having a logic matrix comprising a switching arrangement for switching the logic matrix between a low power, stand-by mode, and a high power, full speed operation mode. Also included is a switch operating circuit responsive to at least one of a internally generated wake-up pulse and an externally generated wake-up pulse for operating the switching arrangement so that the logic matrix is switched between the low power and high power modes. Also included is an internal wake-up pulse generating circuit for generating a wake-up pulse in dependence upon different processing requirements. A programmable power level select circuit provides the ability so select different discrete levels of power in the high power mode.
According to certain preferred embodiments of the present invention, a selected combination of input signals, such as a dedicated product term or address, can be employed to generate the wake-up pulse internally of the logic matrix. Additionally, the matrix is provided with a dedicated input responsive to an externally generated wake-up pulse. Alternatively, the selection of the power mode of the logic circuit can be facilitated by a fused link or E/EE-programmable cell which permits the operation of the logic matrix in a selected mode either permanently, i.e. fuse link, or quasi permanently, i.e. E/EE CMOS process.
Other objects, advantages and novel features of the present invention will become apparent from the following detailed description of the invention when considered in conjunction with the accompanying drawings.